The use of digital flipflop circuits abound in modern electronic systems. In high speed applications, for example frequency synthesizers operating at say one GHz and above, the switching performance of the flipflop circuit becomes an important consideration. Accordingly, many conventional flipflop circuits use only n-channel devices for the inherent higher switching speed associated therewith. Most, if not all, such flipflop circuits using a sole n-channel transistor embodiment include a conventional differential input stage with a constant current source for providing a tail current. Unfortunately, the tail current source continues to flow through the differential input stage even in DC standby mode when the clock signal is between transitions. Thus, regardless of the operational state of the flipflop circuit, the tail current source causes excessive power consumption. It is desirable to eliminate the constant current source and thereby reduce the average power consumption, especially in applications relying on battery power.
An alternate approach to overcome the constant current flow might involve the use of complementary MOS or FET logic, wherein p-channel and n-channel transistors are serially coupled between the power supply rails. The gates of the p-channel and n-channel transistors are driven by a common data input signal and the output is taken at the interconnection of the drains. Due to the complementary operation, one transistor conducts while the other is off, hence, the complementary configuration does not draw DC current in the standby mode between transitions of the clock signal. To implement a flipflop circuit with complementary transistors, it is common in the prior art to further couple at least a second p-channel transistor and n-channel transistor in the serial conduction path between the power supply rails for providing a gating function in response to clock signals CLK and CLK, respectively. Yet, the two p-channel transistors in series significantly reduces the switching speed and operational bandwidth of the flipflop circuit, possibly to a point where it becomes unusable in high speed applications. Therefore, while conventional complementary flipflop circuits appear to solve the current drain problem in standby mode, such designs typically suffer in high speed operation due to the inherent slower switching rate of at least two p-channel transistors serially coupled between the power supply conductors.
Hence, there is a need for an improved flipflop circuit combining high speed operation with substantially zero standby current drain.